Hello.
I want to acess PSTATE.{D, A, I, F} at EL0 on my raspberry Pi 5.
According to the Arm AArch64 Registers Documentation, SCTLR_EL1.UMA = 1 allows user space PSTATE.{D, A, I, F} access.
I have added the following code in init/main.c start_kernel():dmesg print:
[ 0.000000] ------before writing, SCTLR_EL1 = 34e4d91d
[ 0.000000] ++++++after writing, SCTLR_EL1 = 34e4d91d
UMA (bit 9) is not written successfully!
How could this happen?
Does anyone have any idea about this?
Thanks in advance.
I want to acess PSTATE.{D, A, I, F} at EL0 on my raspberry Pi 5.
According to the Arm AArch64 Registers Documentation, SCTLR_EL1.UMA = 1 allows user space PSTATE.{D, A, I, F} access.
But After setting SCTLR_EL1.UMA = 1, msrdaifset, #0xf still generates SIGILL at user space.UMA, bit [9]
User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from AArch64 state only, reported using an ESR_ELx.EC value of 0x18.
I have added the following code in init/main.c start_kernel():
Code:
void start_kernel(void){char *command_line;char *after_dashes;u64 sctlr_el1;pr_info("---__my_boot_flags = 0x%llx\n", __my_boot_flags);sctlr_el1 = read_sysreg(SCTLR_EL1);pr_info("------before writing, SCTLR_EL1 = %llx \n", sctlr_el1);sctlr_el1 |= (1ULL << 9);//turn on UMA, bit [9]write_sysreg(sctlr_el1, SCTLR_EL1);isb();sctlr_el1 = read_sysreg(SCTLR_EL1);pr_info("++++++after writing, SCTLR_EL1 = %llx \n", read_sysreg(SCTLR_EL1));set_task_stack_end_magic(&init_task);...[ 0.000000] ------before writing, SCTLR_EL1 = 34e4d91d
[ 0.000000] ++++++after writing, SCTLR_EL1 = 34e4d91d
UMA (bit 9) is not written successfully!
How could this happen?
Does anyone have any idea about this?
Thanks in advance.
Statistics: Posted by eibisidi — Thu Jan 02, 2025 3:31 am